With the continuous development of semiconductor process technology, process node is gradually reduced and gate-last process has been widely used, to achieve the desired threshold voltage and to improve the performance of device. However, when the critical dimensions of the device further decline, even with the gate-last process, the structure of conventional metal-oxide-semiconductor (MOS) field-effect transistor (FET) has been unable to meet the demand for the device performance, therefore a FinFET as an alternative to a conventional device has been widely concerned.
Referring to FIG. 1, a FinFET fabricated with existing techniques includes: a semiconductor substrate 200 having a protruding fin 201 formed on the semiconductor substrate 200; an isolation layer 205 covering the surface of the semiconductor substrate 200 and part of side walls of the fin 201; a gate structure 203 crossing the fin and covering part of top and side surfaces of the fin 201, and the gate structure 203 includes a gate dielectric layer and a gate electrode on the gate dielectric layer; sidewall spacers 204 formed on both side walls of the gate structure 203; a source region and a drain region formed in the fin 201 at both sides of the gate structure 203 and the sidewall spacers 204.
For such FinFET, the contacting region between the top and both side walls of the fin 201 and the gate structure 203 is a channel region, which is desired to increase the drive current and to improve the performance of the device.
However, in such FinFET fabricated with existing techniques, a source-drain punch-through phenomenon easily appears between the source region and the drain region and affects the performance of the FinFET. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.